A 5.8 GHz Digitally Controlled CMOS Receiver With a Wide Dynamic Range for Chinese ETC System
A 5.8 GHz Digitally Controlled CMOS Receiver With a Wide Dynamic Range for Chinese ETC System
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DOI：
10.1109/tcsii.2017.2777410
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发表时间：
2018-06-01
影响因子：
4.4
通讯作者：
Lu, Chao
中科院分区：
文献类型：
--
作者：
Cao, Lingling;Liu, Ruifeng;Lu, Chao
本简介介绍了一款用于中国电子收费系统的 5.8 GHz 数字控制专用短程通信 (DSRC) 接收器。用于片上自动增益控制的所有 RF、IF 模块和数字基带均集成在 RF 片上系统 (RF-SoC) 上。详细阐述了所提出的数控低噪声放大器（LNA）和混频器电路。测试芯片采用0.13μm CMOS技术实现。接收器中的射频块占用的芯片面积为 0.75 mm(2)。接收器模块在 1.5V 电源电压下消耗 22mA 的电流。测量结果表明，当输入功率电平在-75 dBm至-8 dBm之间变化时，误码率保持优于10-6。该设计使接收器灵敏度提高至少 25%，动态范围提高至少 12%。
This brief presents a 5.8 GHz digitally controlled dedicated short range communications (DSRC) receiver for Chinese electronic toll collection systems. All RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF system-on-chip (RF-SoC). The proposed digitally controlled low noise amplifier (LNA) and mixer circuits are elaborated. The test chip was realized in a 0.13-mu m CMOS technology. The RF blocks in receiver occupy a chip area of 0.75 mm(2). The receiver blocks consume 22 mA under a 1.5-V supply voltage. Measurement results show that the bit error rate maintains better than 10-6, while the input power level varies from -75 dBm to -8 dBm. This design results in a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.