A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue
A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue
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DOI：
10.1109/jssc.2008.917405
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发表时间：
2008-03
影响因子：
5.4
通讯作者：
Minjae Lee;A. Abidi
中科院分区：
文献类型：
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作者：
Minjae Lee;A. Abidi
本文设计了一种类似于粗-细模数转换器（ADC）的粗-细时间-数字转换器（TDC），通过放大时间残差来提高时间分辨率。开发了一种新的数字电路，以比现有解决方案更高的增益（>6）和更大的范围（>80ps）放大时间剩余。然而，采用adc的传统粗精结构并不是tdc的合适解决方案：输入时间不能存储，时间放大器（TA）的增益不能精确控制。本文提出了一种新的粗-细TDC结构，该结构使用一组时间放大器和两个相同的细TDC来补偿转换过程中TA增益的变化。测量的DNL和INL分别为plusmn0.8 LSB和plusmn3 LSB，每1 LSB的值为1.25 ps，而恒定输入的输出代码的标准差在整个TDC范围内保持在1 LSB以下。虽然非线性大于1 LSB，但使用INL查找表或在粗TDC延迟链中更好地匹配延迟将进一步改善线性。
This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.