Power Consumption and Process Variations:Two Challenges to Design of Next-generation ICs
Power Consumption and Process Variations:Two Challenges to Design of Next-generation ICs
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发表时间：
2007
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通讯作者：
L. Zu
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作者：
L. Zu
Intel、AMD、IBM等著名IC厂商的IC技术已进入65 nm，以高性能为目标的高端IC设计面临着成本、设计和测试复杂性等方面的挑战，本文介绍了两个重要而具体的挑战：高功耗和纳米范围内猖獗的工艺变化（PV）。本文包括以下三个部分。首先，接着介绍了IC功耗的构成、高功耗带来的几种负面影响以及主流的低功耗设计方法，接着介绍了工艺偏差的构成、工艺偏差对IC设计的负面影响以及静态延迟分析（STA）研究的统计算法，最后，结合作者的研究工作，简要介绍了下一代集成电路设计中这两个挑战的研究热点。
Famous IC vendors including Intel,AMD,IBM have scaled their IC technologies into 65nm.High-end IC design aiming at high performance has faced many challenges from cost,com- plexities of design and test,and etc.This paper describes two important and detail challenges: High power consumption and rampant process variations(PV)in nanometer regime.This paper includes following three parts.First,it consecutively describes components of IC power con- sumption,several negative influences originated from high power,and mainstream low-power de- sign methods.Second,it consecutively describes components of process variations,their negative influences on IC design,and statistical algorithm that studies about static delay analysis(STA), power analysis,and low-power design.Last,combining with the authors' own research,this pa- per simply presents hot research topics on these two challenges of next-generation IC design.