Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
复制标题
使用影子集群通过硬电路提高 FPGA 的面积效率
DOI：
10.1109/tvlsi.2009.2026651
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发表时间：
2010
影响因子：
2.8
通讯作者：
Jonathan Rose
中科院分区：
文献类型：
--
作者：
P. Jamieson;Jonathan Rose
现场可编程门阵列(现场可编程门阵列)和专用集成电路之间存在着巨大的逻辑密度差距，而这一差距是现场可编程门阵列在大批量应用中成本效益不高的主要原因。现代的现场可编程门阵列通过包括存储器和乘法器等“硬”电路缩小了这一差距，这些电路在使用时非常高效。然而，如果不使用这些硬件电路，它们就会浪费(包括围绕逻辑的非常昂贵的可编程布线)，并对逻辑密度产生负面影响。在本文中，我们提出了一个体系结构的概念，称为阴影簇，它试图减轻这种损失。影子簇是一个标准的现场可编程门阵列逻辑“簇”(通常由一组查找表和触发器组成)，它被放置在每个硬件电路的“后面”，并且可以通过简单的小型多路复用器可编程地在不需要的情况下替换硬件电路。影子集群是有效的，因为到目前为止，在FPGA中，最大的面积成本是用于连接逻辑的可编程路由。影子集群面积成本很小，但它能够在具有不同硬件电路需求的应用中更一致地采用可编程布线。我们引入了新的术语来描述FGPA上硬件电路的经济性，并提供了一种科学的方法来衡量面积有效性。我们测量了带阴影簇和不带阴影簇的现场可编程门阵列的面积效率，结果表明，现代商业体系结构(乘法器与软逻辑的比例固定)使用阴影簇可以获得4.7%的面积效率。事实上，我们在“合理”条件下研究的每一种建筑从未显示出面积效率的损失。此外，我们还表明，采用阴影簇概念的大多数区域高效体系结构比没有影子簇的区域高效体系结构要好12.5%。
There is a dramatic logic density gap between field-programmable gate arrays (FPGAs) and application-specific integrated circuits, and this gap is the main reason FPGAs are not cost-effective in high-volume applications. Modern FPGAs narrow this gap by including “hard” circuits such as memories and multipliers, which are very efficient when they are used. However, if these hard circuits are not used, they go wasted (including the very expensive programmable routing that surrounds the logic), and have a negative impact on logic density. In this paper, we present an architectural concept, called shadow clusters, which seeks to mitigate this loss. A shadow cluster is a standard FPGA logic “cluster” (typically consisting of a group of lookup tables and flip-flops) that is placed “behind” every hard circuit, and can programmably, through simple, small multiplexers, replace the hard circuit in the event it is not needed. A shadow cluster is effective because the largest area cost, by far, in an FPGA is for the programmable routing that connects the logic. The shadow cluster area cost is small, and yet it enables more consistent employment of the programmable routing across applications with varying demand for hard circuits. We introduce new terminology to describe the economics of hard circuits on FGPAs, and provide a scientific way to measure the area effectiveness. We measure the area efficiency of FPGAs with and without shadow clusters, and show that a modern commercial architecture (with a fixed ratio of multipliers to soft logic) would gain 4.7% in area efficiency by employing shadow clusters. Indeed, every architecture we studied under “reasonable” conditions never showed a loss of area efficiency. Furthermore, we show that most area-efficient architecture that employs the shadow cluster concept is 12.5% better than the most area-efficient architecture without shadow clusters.