A low power GPS/Galileo/GLONASS receiver in 65nm CMOS

A low power GPS/Galileo/GLONASS receiver in 65nm CMOS
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DOI：
10.1109/isocc.2013.6864017
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发表时间：
2013-11
期刊：
2013 International SoC Design Conference (ISOCC)
影响因子：
--
通讯作者：
Huijung Kim;Jeong-Hyun Choi;Sang-Yun Lee;Taewan Kim;Jung-woo Kim;Jong-Dae Bae;Chaehag Yi;Hyunwon Moon
Huijung Kim;Jeong-Hyun Choi;Sang-Yun Lee;Taewan Kim;Jung-woo Kim;Jong-Dae Bae;Chaehag Yi;Hyunwon Moon
中科院分区：
其他
文献类型：
--
作者：
Huijung Kim;Jeong-Hyun Choi;Sang-Yun Lee;Taewan Kim;Jung-woo Kim;Jong-Dae Bae;Chaehag Yi;Hyunwon Moon

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A low power GPS/Galileo/GLONASS receiver is presented. The single chip supports GPS/Galileo and GLONASS operation simultaneously. To operate both application simultaneously, two mixers and two baseband filters are used. The chip size is 3.24 mm2 including bonding PAD. The system noise figure (NF) is 1.95 dB including SAW filter which loss is 1 dB. Power consumption is 23.6 mW for GPS/Galileo operation and 25.4 mW for GLONASS operation from 1.2V supply.