DCA: A DRAM-cache-Aware DRAM Controller
DCA: A DRAM-cache-Aware DRAM Controller
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DOI：
10.1109/sc.2016.75
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发表时间：
2016-11
期刊：
影响因子：
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通讯作者：
Cheng-Chieh Huang;V. Nagarajan;Arpit Joshi
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文献类型：
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作者：
Cheng-Chieh Huang;V. Nagarajan;Arpit Joshi
3D堆叠技术实现了在处理器上嵌入大型DRAM缓存的选项。由于DRAM高速缓存可以比传统的SRAM高速缓存大几个数量级，因此其高速缓存标签的大小也可以很大。最近的研究已经提出将这些标签存储在堆叠式DRAM阵列本身中。然而，这增加了DRAM缓存请求的复杂性，这现在转换为多个DRAM缓存访问(标签/数据)。在这项工作中，我们解决了如何调度这些DRAM缓存访问。我们从探索传统的DRAM控制器是否能很好地工作开始。我们介绍了两种可能的基线设计，并研究了它们的局限性。然后，我们推导出一组DRAM高速缓存控制器必须理想地满足的设计原则。我们的DRAM缓存感知(DCA)DRAM控制器基于这些原则，可持续提高各种DRAM缓存组织的性能。
3D-stacking technology has enabled the option of embedding a large DRAM cache onto the processor. Since the DRAM cache can be orders of magnitude larger than a conventional SRAM cache, the size of its cache tags can also be large. Recent works have proposed storing these tags in the stacked DRAM array itself. However, this increases the complexity of a DRAM cache request, which now translates into multiple DRAM cache accesses (tag/data). In this work, we address how to schedule these DRAM cache accesses. We start by exploring whether or not a conventional DRAM controller will work well. We introduce two potential baseline designs and study their limitations. We then derive a set of design principles that a DRAM cache controller must ideally satisfy. Our DRAM-cache-aware (DCA) DRAM controller, that is based on these principles, consistently improves performance over various DRAM cache organizations.