A transition probability based delay measurement method for arbitrary circuits on FPGAs
A transition probability based delay measurement method for arbitrary circuits on FPGAs
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一种基于转移概率的 FPGA 上任意电路延迟测量方法
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
P. Cheung
中科院分区：
文献类型：
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作者：
Justin S. J. Wong;N. P. Sedcole;P. Cheung
本文提出了一种新的测试方法，用于测量FPGA上任何电路的最坏情况路径延迟，无论是组合电路还是顺序电路，在这种情况下，几乎不需要事先了解电路的内部结构。该方法是基于检测电路输出节点上的转移概率分布的变化，而测试时钟频率的范围是逐步通过。该方法适用于三类电路，全部在Altera Cyclone III FPGA上实现：加法器进位链，嵌入式乘法器和线性反馈移位寄存器。将测量到的延迟与之前发表的方法进行比较，但更耗时，结果匹配度在12%以内。
This paper proposes a novel test method for measuring the worst case path delay of any circuit on an FPGA, combinatorial or sequential, where little prior knowledge of the circuitpsilas internal structure is required. The method is based on detecting changes in the transition probability profile on the circuitpsilas output nodes while a range of test clock frequencies is stepped through. The method is applied to three classes of circuits, all implemented on an Altera Cyclone III FPGA: an adder carry chain, an embedded multiplier and a linear-feedback shift-register. The measured delays are compared to that found by a previously published, but much more time consuming, method and their results match to within 12%.