Realistic fault extraction for high-quality design and test of VLSI systems
Realistic fault extraction for high-quality design and test of VLSI systems
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真实故障提取，用于 VLSI 系统的高质量设计和测试
DOI：
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发表时间：
1997
期刊：
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通讯作者：
João Paulo Teixeira
中科院分区：
文献类型：
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作者：
F. Gonçalves;I. Teixeira;João Paulo Teixeira
本文的目的是提出一种用于电路和现实故障提取的方法，以及将其在新工具Lobs中实现，将包含在虚拟测试环境DotLab中。在CMO，双极或BICMOS技术中实现的数字，模拟和混合信号IC在曼哈顿和45/ SPL DEG/几何形状都处理。在自上而下的设计流中获得的更高级别的设计数据用于现实的故障表征。扩展了滑动窗口算法以提取非正交几何形状的故障。提出了一种准确的临界区域评估算法来计算出现缺陷的可能性。分析了超过100,000个晶体管IC的桥接缺陷。
The purpose of this paper is to present a methodology for circuit and realistic fault extraction, and its implementation in a new tool, lobs, to be included in a virtual test environment, DOTLab. Digital, analog and mixed signal ICs, implemented in CMOS, bipolar or BiCMOS technologies are handled both in Manhattan and 45/spl deg/ geometries. Higher level design data, obtained in the top-down design flow, is used for realistic fault characterization. A sliding window algorithm is extended for fault extraction of non-orthogonal geometries. An accurate critical area evaluation algorithm is proposed to compute the probability of occurrence of the defects. Over 100,000 transistor ICs are analyzed for bridging defects.