Fault-tolerance thresholds for the surface code with fabrication errors
Fault-tolerance thresholds for the surface code with fabrication errors
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DOI：
10.1103/physreva.96.042316
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发表时间：
2017-10-12
影响因子：
2.9
通讯作者：
Browne, Dan E.
中科院分区：
文献类型：
--
作者：
Auger, James M.;Anwar, Hussain;Browne, Dan E.
拓扑纠错码的构造要求能够在具有非平凡拓扑的流形上嵌入物理量子位的晶格，从而使量子信息在流形的全局自由度（即拓扑）中编码。然而，大规模拓扑器件的制造无疑会受到制造错误的影响——永久性的缺陷组件，如缺少物理量子比特或失败的纠缠门——将永久性缺陷引入晶格的拓扑结构，从而大大减少编码距离和编码逻辑量子比特的质量。在这项工作中，我们研究了制造误差如何影响拓扑码的性能，使用表面码作为测试平台。一种已知的减轻缺陷晶格的方法涉及在长序列的综合征提取电路中使用原始SWAP门。相反，我们表明，在存在制造误差的情况下，可以使用supercheck算子方法和有缺陷的表稳定器发生器的结果来确定该综合征，而无需任何额外的计算开销或使用SWAP门。我们使用基于电路的噪声模型和最小权重完美匹配解码器，报告了存在量子比特制造和门制造错误的数值容错阈值。我们的数值分析最适用于基于二维芯片的技术，但这里提出的技术可以很容易地扩展到其他拓扑体系结构。我们发现，在存在8%量子比特制造误差的情况下，表面代码仍然可以容忍高达0.1%的计算错误率。
The construction of topological error correction codes requires the ability to fabricate a lattice of physical qubits embedded on a manifold with a nontrivial topology such that the quantum information is encoded in the global degrees of freedom (i.e., the topology) of the manifold. However, the manufacturing of large-scale topological devices will undoubtedly suffer from fabrication errors-permanent faulty components such as missing physical qubits or failed entangling gates-introducing permanent defects into the topology of the lattice and hence significantly reducing the distance of the code and the quality of the encoded logical qubits. In this work we investigate how fabrication errors affect the performance of topological codes, using the surface code as the test bed. A known approach to mitigate defective lattices involves the use of primitive SWAP gates in a long sequence of syndrome extraction circuits. Instead, we show that in the presence of fabrication errors the syndrome can be determined using the supercheck operator approach and the outcome of the defective gauge stabilizer generators without any additional computational overhead or use of SWAP gates. We report numerical fault-tolerance thresholds in the presence of both qubit fabrication and gate fabrication errors using a circuit-based noise model and the minimum-weight perfect-matching decoder. Our numerical analysis is most applicable to two-dimensional chip-based technologies, but the techniques presented here can be readily extended to other topological architectures. We find that in the presence of 8% qubit fabrication errors, the surface code can still tolerate a computational error rate of up to 0.1%.