Missing the Memory Wall: The Case for Processor/Memory Integration
Missing the Memory Wall: The Case for Processor/Memory Integration
复制标题
缺少内存墙：处理器/内存集成案例
DOI：
--
复制
发表时间：
1996
期刊：
影响因子：
--
通讯作者：
A. Nowatzyk
中科院分区：
文献类型：
--
作者：
Ashley Saulsbury;Fong Pong;A. Nowatzyk
当前的高性能计算机系统使用复杂的大型超标量CPU，其通过高速缓存和互连系统的层次结构与主存储器接口。这些以CPU为中心的设计投入了大量的功率和芯片面积，以弥合CPU和主存速度之间不断扩大的差距。然而，许多大型应用程序不运行在这些系统上，并受到内存子系统performance.This本文主张一个集成系统的方法，使用不太强大的CPU，与先进的内存技术紧密结合，建立具有竞争力的系统，大大降低了成本和复杂性。基于下一代0.25米，256 Mbit的动态随机存取存储器（DRAM）的过程和现有机器的分析，我们表明，处理器存储器集成可以用来建立有竞争力的，可扩展的和成本效益的MP systems.We目前的结果从执行驱动的单和多处理器的模拟显示，低延迟和高带宽的好处可以补偿的限制的大小和复杂性的集成处理器的设计研究。在该系统中，具有长行的小型直接映射指令高速缓存非常有效，因为用牺牲高速缓存增强的列缓冲器数据高速缓存也是如此。
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-centric designs invest a lot of power and chip area to bridge the widening gap between CPU and main memory speeds. Yet, many large applications do not operate well on these systems and are limited by the memory subsystem performance.This paper argues for an integrated system approach that uses less-powerful CPUs that are tightly integrated with advanced memory technologies to build competitive systems with greatly reduced cost and complexity. Based on a design study using the next generation 0.25µm, 256Mbit dynamic random-access memory (DRAM) process and on the analysis of existing machines, we show that processor memory integration can be used to build competitive, scalable and cost-effective MP systems.We present results from execution driven uni- and multi-processor simulations showing that the benefits of lower latency and higher bandwidth can compensate for the restrictions on the size and complexity of the integrated processor. In this system, small direct mapped instruction caches with long lines are very effective, as are column buffer data caches augmented with a victim cache.