Dynamic SEU Sensitivity of Designs on Two 28-nm SRAM-Based FPGA Architectures
Dynamic SEU Sensitivity of Designs on Two 28-nm SRAM-Based FPGA Architectures
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DOI：
10.1109/tns.2017.2772288
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发表时间：
2018
影响因子：
1.8
通讯作者：
Andrew M. Keller;Tim A. Whiting;Kenneth B. Sawyer;M. Wirthlin
中科院分区：
文献类型：
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作者：
Andrew M. Keller;Tim A. Whiting;Kenneth B. Sawyer;M. Wirthlin
在两种不同的基于28纳米静态随机存取存储器的FPGA （Intel Stratix V和Xilinx Kintex 7 FPGA）上测试了两种现场可编程门阵列（FPGA）的动态单事件干扰（SEU）灵敏度。这些设计在传统的非缓解版本和具有反馈三重模块冗余（TMR）的容忍seu版本中进行了测试。通过中子辐射测试，发现两种器件的未减设计灵敏度和低能级器件灵敏度相近。结果还表明，反馈TMR和组态洗涤对两种fpga的设计都有好处。虽然TMR是有帮助的，但TMR的好处取决于设计结构和器件体系结构。TMR和洗井将动态SEU的灵敏度降低了4 ~ 54倍。
Two field-programmable gate array (FPGA) designs are tested for dynamic single event upset (SEU) sensitivity on two different 28-nm static random access memory-based FPGAs—an Intel Stratix V and a Xilinx Kintex 7 FPGA. These designs were tested in both a conventional unmitigated version and a version to tolerate SEUs with feedback triple modular redundancy (TMR). The unmitigated design sensitivity and the low-level device sensitivity were found to be similar between the devices through neutron radiation testing. Results also show that feedback TMR and configuration scrubbing benefit both designs on both FPGAs. While TMR is helpful, the benefit of TMR depends on the design structure and the device architecture. TMR and scrubbing reduced dynamic SEU sensitivity by a factor of 4– $54\times $ .