Modelling and Analysis of FPGA-based MPSoC System with Multiple DNN Accelerators
Modelling and Analysis of FPGA-based MPSoC System with Multiple DNN Accelerators
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DOI：
10.1109/newcas57931.2023.10198162
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发表时间：
2023-06
期刊：
影响因子：
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通讯作者：
Cong Gao;Xuqi Zhu;S. Saha;K. Mcdonald-Maier;X. Zhai
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文献类型：
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作者：
Cong Gao;Xuqi Zhu;S. Saha;K. Mcdonald-Maier;X. Zhai
深度神经网络（DNN）几十年来已广泛应用于许多领域，将其部署在嵌入式系统上的标准方法是使用加速器。然而，由于嵌入式系统的资源限制，提高能源和计算效率成为该领域的研究挑战之一。 DNN模型优化和NAS（神经架构搜索）通常用于增强DNN模型在嵌入式系统上的运行效率。然而，由于系统运行时工作负载在实际情况下是存在差异的，为了进一步提高系统运行时的计算效率，需要进行实时的软硬件设计空间探索，以保证系统运行时运行在最佳时间状态。本文提出了一种全面的建模和分析方法，用于从配备多个 DNN 加速器的 AMD-Xilinx 异构 MPSoC 平台收集性能数据（例如延迟、能耗、准确性等）。结果表明，准确性损失、硬件性能和模型大小之间的关系显着相关。此外，可以通过在运行时给出约束来获得适当的硬件和软件配置。
Deep Neural Networks (DNNs) have been widely applied in many fields for decades, and a standard method for deploying them on embedded systems involves using accelerators. However, due to the resource constraints of embedded systems, improving energy and computing efficiency becomes one of the research challenges in this domain. DNN model optimization and NAS (Neural Architecture Searching) are commonly used to strengthen the DNN model running efficiency on an embedded system. However, because the system’s runtime workloads are varied in practical situations, to further improve the computing efficiency of the system at runtime, real-time hardware and software design space exploration is required to ensure the system is running at the optimal time state at runtime. This paper presents a comprehensive modelling and analysis approach for the performance data (e.g., latency, energy consumption, accuracy, etc.) collected from an AMD-Xilinx heterogeneous MPSoC platform equipped with multiple DNN accelerators. The results demonstrate that the relationships between accuracy loss, hardware performance, and model size are significantly correlated. Furthermore, an appropriate hardware and software configuration could be obtained by giving constraints at runtime.