A Superjunction U-MOSFET With SIPOS Pillar Breaking Superjunction Silicon Limit by TCAD Simulation Study
A Superjunction U-MOSFET With SIPOS Pillar Breaking Superjunction Silicon Limit by TCAD Simulation Study
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DOI：
10.1109/led.2017.2694842
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发表时间：
2017-06-01
影响因子：
4.9
通讯作者：
Yang, Yintang
中科院分区：
文献类型：
--
作者：
Cao, Zhen;Duan, Baoxing;Yang, Yintang
提出了一种新型的半绝缘多晶硅柱超导垂直UMOSFET(SIPOS SJ-UMOS)，并通过TCAD模拟对其机理进行了研究。关态时，SIPOS柱的整形效应增强了垂直电场强度，削弱了横向电场分量，提高了击穿电压(BV)。此外，由于SIPOS柱的耗尽增强，导致低比导通电阻(R-ON，(SP))，因此高掺杂N柱被允许用于所提出的器件。在导通状态下，在漂移区中形成累积层，导致RON，sp.的额外降低。模拟结果表明，与相同漂移长度的常规SJ-UMOS相比，该器件的RON、SP降低了59%，BV提高了16.7%，同时突破了SJ-UMOS的硅极限。此外，SIPOS SJ-UMOS的充电不平衡耐久性也得到了提高。
A novel superjunction (SJ) vertical UMOSFET with semi-insulating POly-crystalline silicon pillar (SIPOS SJ-UMOS) is proposed and its mechanism is investigated by TCAD simulations. In the off-state, the reshape effect of SIPOS pillars enhances the vertical electric field strength and weakens the lateral field component, which increases the breakdown voltage (BV). In addition, the highly doped N-pillars are allowed for the proposed device due to the enhanced depletion by the SIPOS pillars, which leads to a low specific ON resistance (R-ON, (sp)). In the on-state, an accumulation layer is formed in drift region leading to an additional reduction in the RON, sp. Simulation results show that the RON, sp decreases 59%, and BV increases by 16.7%, simultaneously, breaking the SJ silicon limit, comparedwith those of a conventionalSJ-UMOS with the same drift length. Moreover, the charge-imbalance endurance of SIPOS SJ-UMOS is also improved.