DESIGN OF A PARALLEL VLSI PROCESSOR FOR ROAD EXTRACTION BASED ON LOGIC-IN-MEMORY ARCHITECTURE
DESIGN OF A PARALLEL VLSI PROCESSOR FOR ROAD EXTRACTION BASED ON LOGIC-IN-MEMORY ARCHITECTURE
复制标题
基于内存逻辑架构的道路提取并行VLSI处理器设计
DOI：
10.9746/sicetr1965.36.1009
复制
发表时间：
2000
期刊：
影响因子：
--
通讯作者：
M. Kameyama
中科院分区：
文献类型：
--
作者：
T. Kudoh;T. Hanyu;M. Kameyama
This paper describes the design of a road extraction VLSI (Very Large Scale Integration) processor that is designed to keep the data transfer bottleneck between processing elements to a minimum. It involves a algorithm that is based on parallel processing and logic- in-memory architecture.
