Implementation of FPGA-based level-1 tracking at CMS for the HL-LHC
Implementation of FPGA-based level-1 tracking at CMS for the HL-LHC
复制标题
在 HL-LHC 的 CMS 上实现基于 FPGA 的 1 级跟踪
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
J. Chaves
中科院分区：
文献类型：
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作者：
J. Chaves
提出了一种新的航迹重构方法，用于CMS触发器的全硬件第一级。该方法的应用是为了升级的全硅跟踪器，这是要安装的LHC（HL-LHC）的高亮度时代。升级后的LHC机器预计将提供约5 × 1034 cm−2s−1的光度。这个预期的亮度意味着在40 MHz的频率下，每个聚束交叉中将有大约125个堆积事件。为了在这些条件下将CMS触发率保持在可管理的水平，有必要对将要处理的事件做出快速决策。该算法的时序估计值预计低于5 μs，完全符合CMS的L1触发器对航迹识别的要求。该算法是基于整数的，允许它在FPGA上实现。目前，我们正在使用Xilinx Virtex 6 FPGA进行演示硬件实现。在C++和Verilog的仿真结果显示的数据吞吐量和参数分辨率方面的算法性能。
A new approach for track reconstruction is presented to be used in the all-hardware first level of the CMS trigger. The application of the approach is intended for the upgraded all-silicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The upgraded LHC machine is expected to deliver a luminosity on the order of 5 × 1034 cm−2s−1. This expected luminosity means there would be about 125 pileup events in each bunch crossing at a frequency of 40 MHz. To keep the CMS trigger rate at a manageable level under these conditions, it is necessary to make quick decisions on the events that will be processed. The timing estimates for the algorithm are expected to be below 5 μs, well within the requirements of the L1 trigger at CMS for track identification. The algorithm is integer-based, allowing it to be implemented on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA. Results from simulations in C++ and Verilog are presented to show the algorithm performance in terms of data throughput and parameter resolution.