Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures
Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures
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DOI：
10.1038/nature02674
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发表时间：
2004-07-01
期刊：
影响因子：
64.8
通讯作者：
Lieber, CM
中科院分区：
文献类型：
--
作者：
Wu, Y;Xiang, J;Lieber, CM
大量的努力已经放在开发半导体碳纳米管（1-3）和纳米线（4）作为电子器件的构建块，如场效应晶体管，可以取代传统的硅晶体管在混合电子或导致独立的纳米系统（4，5）。将电触点连接到单个器件是实现集成的第一步，并且已经使用光刻限定的金属电极解决了该步骤（1- 4，6 -8）。然而，这些金属接触限定了比纳米级构建块大得多的尺寸尺度，因此限制了许多潜在的优点。在这里，我们报告了一个集成的接触和互连解决方案，克服了这种尺寸限制，通过选择性的硅纳米线转化为金属硅化镍（NiSi）纳米线。电测量表明，单晶硅化镍纳米线具有约10 μ Ω cm的理想介电常数和显著高的失效电流密度，> 10（8）A cm（-2）。此外，我们展示了硅化镍/硅（NiSi/Si）纳米线异质结构与原子级尖锐的金属-半导体界面的制造。我们生产的场效应晶体管的基础上，其中的源极-漏极接触的金属NiSi纳米线区域定义的异质结构。我们的方法与传统的平面硅电子器件完全兼容，并且可以使用交叉纳米线架构扩展到10 nm规模。
Substantial effort has been placed on developing semiconducting carbon nanotubes(1-3) and nanowires(4) as building blocks for electronic devices-such as field-effect transistors-that could replace conventional silicon transistors in hybrid electronics or lead to stand-alone nanosystems(4,5). Attaching electric contacts to individual devices is a first step towards integration, and this step has been addressed using lithographically defined metal electrodes(1-4,6-8). Yet, these metal contacts define a size scale that is much larger than the nanometre-scale building blocks, thus limiting many potential advantages. Here we report an integrated contact and interconnection solution that overcomes this size constraint through selective transformation of silicon nanowires into metallic nickel silicide (NiSi) nanowires. Electrical measurements show that the single crystal nickel silicide nanowires have ideal resistivities of about 10 muOmega cm and remarkably high failure-current densities, > 10(8) A cm(-2). In addition, we demonstrate the fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal-semiconductor interfaces. We produce field-effect transistors based on those heterostructures in which the source-drain contacts are defined by the metallic NiSi nanowire regions. Our approach is fully compatible with conventional planar silicon electronics and extendable to the 10-nm scale using a crossed-nanowire architecture.