Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications
Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications
复制标题
使用经过 40 纳米节点 2Gb DRAM 验证的 300 毫米晶圆，超薄至 4 微米，适用于 3D 多堆栈 WOW 应用
DOI：
10.1109/vlsit.2014.6894347
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
T. Ohba
中科院分区：
文献类型：
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作者：
Y. Kim;S. Kodama;Y. Mizushima;N. Maeda;H. Kitada;K. Fujimoto;T. Nakamura;D. Suzuki;A. Kawai;K. Arai;T. Ohba
经过40纳米节点2 GB动态随机存取存储器验证，使用300 mm晶片的超薄到4μm已经首次被开发出来。对粗磨、精磨和应力消除三种不同的减薄工艺进行了优化，在晶片背面形成了深度小于10 nm的原子级空位。即使在薄化到4-μm之后，厚度均匀度在300 mm的晶片内也约为1-μm。在采用2 GB DRAM晶片的超薄后，没有发现在保持特性和分布方面的劣化。这表明，包括晶片键合和剥离步骤在内的减薄过程没有发生损坏。这些结果表明，具有最低TSV长宽比和寄生电容的多堆栈片上晶圆(WOW)工艺具有很好的可行性，并实现了T级高密度存储器的多堆栈。
An ultra-thinning down to 4-μm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-μm was approximately 1-μm within 300-mm wafer. No degradation in terms of retention characteristics and distribution employing 2Gb DRAM wafer was found after ultra-thinning. This suggests that no damage occurred due to thinning processes including wafer bonding and debonding steps. These results indicate good feasibility for multi-stack Wafer-on-Wafer (WOW) processes with the lowest aspect ratio of TSVs and parasitic capacitance, and enable multi-stacking for Tera-scale high density memory.