Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect
Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect
复制标题
总电离剂量效应下 16nm MLC NAND 闪存的错误表征和缓解
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
Jehoshua Bruck
中科院分区：
文献类型：
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作者：
Yue Li;D. Sheldon;A. S. Ramos;Jehoshua Bruck
研究了16 nm MLC NAND闪存在总电离剂量(TID)效应下的系统级可靠性。在TID影响下的零件中发生的误差在多个层次上被表征。结果表明，数据的忠实恢复只持续到9k rad。在辐照闪光样品中观察到的数据误差是强烈不对称的。为了提高零件的可靠性，我们研究了考虑TID误差特性的误差抑制方法。首先，我们实现了一种新颖的数据表示方案，该方案使用单元电压的相对顺序来存储数据。该表示法对浮动门的均匀非对称阈值电压漂移具有更强的鲁棒性。实验结果表明，对于编程/擦除周期小于3k的块和10krad的块，该方案的误码率至少降低50%。其次，我们对内存擦除方案进行了实验评估。基于结果，我们确定了一种在不进行块擦除的情况下刷新单元的方案。评估结果表明，该擦洗方案下的部件可以承受高达8k/s的总剂量和57k rad的总剂量。
This paper studies the system-level reliability of 16nm MLC NAND flash memories under total ionizing dose (TID) effect. Errors that occur in the parts under TID effect are characterized at multiple levels. Results show that faithful data recovery only lasts until 9k rad. Data errors observed in irradiated flash samples are strongly asymmetric. To improve the reliability of the parts, we study error mitigation methods that consider the specific properties of TID errors. First, we implement a novel data representation scheme that stores data using the relative order of cell voltages. The representation is more robust against uniform asymmetric threshold voltage shift of floating gates. Experimental results show that the scheme reduces errors at least by 50% for blocks with less than 3k program/erase cycles and 10k rad. Second, we conduct empirical evaluations of memory scrubbing schemes. Based on the results, we identify a scheme that refreshes cells without doing block erasure. Evaluation results show that parts under this scrubbing scheme survive up to 8k PECs and 57k rad total doses.