Attenuation of single event induced pulses in CMOS combinational logic
Attenuation of single event induced pulses in CMOS combinational logic
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DOI：
10.1109/23.659038
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发表时间：
1997-12-01
影响因子：
1.8
通讯作者：
Buchner, SP
中科院分区：
文献类型：
--
作者：
Baze, MP;Buchner, SP
本文介绍了使用常见数字 CMOS 设计实践构建的组合逻辑结构中 SEU 生成的瞬态脉冲衰减的研究结果。 SPICE 电路分析、重离子测试和脉冲聚焦激光模拟用于检查长逻辑串中瞬态脉冲行为的响应特性。结果表明，虽然存在可观察到的影响，但一般不能假设衰减会显着降低观察到的电路误码率。
Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.