Scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technologies
Scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technologies
复制标题
将混合信号神经形态处理器扩展到 28 nm FD-SOI 技术
DOI：
10.1109/biocas.2016.7833854
复制
发表时间：
2016
期刊：
影响因子：
--
通讯作者：
G. Indiveri
中科院分区：
文献类型：
--
作者：
Ning Qiao;G. Indiveri
随着工艺规模的不断扩大，深亚微米混合信号设计变得越来越具有挑战性。在本文中，我们提出了一个分析的缩放多核混合信号神经形态处理器先进的28纳米FD-SOI节点。我们解决了模拟设计问题所产生的使用先进的工艺，包括大的漏电流和器件失配的问题，以及异步数字设计问题。我们提出的结果的Monte Carlo分析和电路模拟的neuromorphic亚阈值模拟/数字神经元电路再现生物学上合理的反应。我们描述了AER用于实现基于PCHB的异步QDI路由过程中的多核神经形态架构，并通过电路仿真结果验证其操作。最后，我们描述了这些多核神经形态处理器中使用的定制28纳米CAM为基础的存储器资源的实现，并讨论了通过使用先进的RRAM器件集成在28纳米全耗尽绝缘体上硅（FD-SOI）工艺中增加密度的可能性。
As processes continue to scale aggressively, the design of deep sub-micron, mixed-signal design is becoming more and more challenging. In this paper we present an analysis of scaling multi-core mixed-signal neuromorphic processors to advanced 28 nm FD-SOI nodes. We address analog design issues which arise from the use of advanced process, including the problem of large leakage currents and device mismatch, and asynchronous digital design issues. We present the outcome of Monte Carlo Analysis and circuit simulations of neuromorphic sub threshold analog/digital neuron circuits which reproduce biologically plausible responses. We describe the AER used to implement PCHB based asynchronous QDI routing processes in multi-core neuromorphic architectures and validate their operation via circuit simulation results. Finally we describe the implementation of custom 28 nm CAM based memory resources utilized in these multi-core neuromorphic processor and discuss the possibility of increasing density by using advanced RRAM devices integrated in the 28 nm Fully-Depleted Silicon on Insulator (FD-SOI) process.