Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers.
Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers.
复制标题
设计和实现用于处理心脏起搏器中心电图的超低能耗 FFT ASIC。
DOI：
10.1109/tvlsi.2018.2883642
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发表时间：
2019
影响因子：
2.8
通讯作者：
Panday,ManojM
中科院分区：
文献类型：
--
作者：
Mostafa,Safwat;John,EugeneB;Panday,ManojM
在嵌入式生物医学应用中，快速傅立叶变换（FFT）等频谱分析算法对于模式检测至关重要，并且一直是持续研究的焦点。在心脏起搏器等深度嵌入式系统中，基于FFT的信号处理通常由专用集成电路（ASIC）计算，以实现低功耗操作。本简报提出了一种用于FFT ASIC解决方案的数据驱动设计方法，该方法利用了这些嵌入式系统遇到的有限数据范围。本简报中提出的优化使用散列和查找表的简单概念，以有效地减少执行心电图（ECG）信号FFT所需的算术运算的数量。通过降低FFT计算的动态功耗和总体能量占用，所提出的设计旨在为心脏起搏器实现更长的电池寿命。该设计是综合使用90纳米标准单元库，门级开关活动进行了模拟，以获得准确的功耗结果。所提出的优化实现了每个FFT 27.72 nJ的低能耗，当使用从PhysioNet收集的实际ECG数据进行测试时，比标准的128点基-2 FFT低14.22%。
In embedded biomedical applications, spectrum analysis algorithms such as fast Fourier transform (FFT) are crucial for pattern detection and have been the focus of continued research. In deeply embedded systems such as cardiac pacemakers, FFT-based signal processing is typically computed by application-specific integrated circuit (ASIC) to achieve low-power operation. This brief proposes a data-driven design approach for an FFT ASIC solution, which exploits the limited range of data encountered by these embedded systems. The optimizations proposed in this brief use the simple concept of hashing and lookup table to effectively reduce the number of arithmetic operations required to perform the FFT of an electrocardiogram (ECG) signal. By reducing the dynamic power consumption and overall energy footprint of FFT computation, the proposed design aims to achieve longer battery life for a cardiac pacemaker. The design is synthesized using a 90-nm standard cell library, and gate level switching activity is simulated to obtain accurate power consumption results. The proposed optimizations achieved a low energy consumption of 27.72 nJ per FFT, which is 14.22% lower than a standard 128-point radix-2 FFT when tested with actual ECG data collected from PhysioNet.