Metal Reaction-Induced Bulk-Doping Effect in Forming Conductive Source-Drain Regions of Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors
Metal Reaction-Induced Bulk-Doping Effect in Forming Conductive Source-Drain Regions of Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors
复制标题
金属反应引起的体掺杂效应形成自对准顶栅非晶InGaZnO薄膜晶体管的导电源漏区
DOI：
10.1021/acsami.0c21123
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发表时间：
2021-02-16
影响因子：
9.5
通讯作者：
Zhang, Shengdong
中科院分区：
文献类型：
--
作者：
Yang, Huan;Zhou, Xiaoliang;Zhang, Shengdong
本文系统地研究了铝（Al）处理引起的掺杂对自对准顶栅（SATG）非晶氧化铟镓锌（a-InGaZnO或a-IGZO）薄膜晶体管（TFT）导电源漏（SD）区形成的影响。 Al 反应掺杂导致平均载流子浓度超过 1 x 10(20) cm(-3)，薄层电阻约为 500 Omega/sq。结果表明，尽管表面经过处理，掺杂效应仍然很大。据公开，掺杂过程是化学氧化还原反应，其在金属/a-IGZO界面处产生氧空位和金属间隙缺陷。产生的氧空位和金属填隙都充当浅施主，氧空位迅速扩散，导致体掺杂效应。所制作的具有Al反应掺杂SD区域的SATG a-IGZO TFT表现出高性能和优异的稳定性，具有约10 Omega cm的低宽度归一化SD电阻、13 cm(2)/(V s)的良好饱和迁移率、低于1 x 10(-13) A的关断电流、0.5 V的阈值电压、-0.02 V的轻微滞后和小于0.1 V 30 V 栅极偏置应力下的阈值电压漂移持续 2000 秒。
In this paper, the aluminum (Al) treatment-induced doping effect on the formation of conductive source-drain (SD) regions of self-aligned top-gate (SATG) amorphous indium gallium zinc oxide (a-InGaZnO or a-IGZO) thin-film transistors (TFTs) is systematically investigated. Average carrier concentration over 1 x 10(20) cm(-3) and sheet resistance of around 500 Omega/sq result from the Al reaction doping. It is shown that the doping effect is of bulk despite the treatment at the surface. The doping process is disclosed to be a chemical oxidation-reduction reaction, that generates defects of oxygen vacancies and metal interstitials at the metal/a-IGZO interface. Both the generated oxygen vacancies and metal interstitials act as shallow donors, and the oxygen vacancies diffuse rapidly, leading to the bulk-doping effect. The fabricated SATG a-IGZO TFTs with the Al reaction-doped SD regions exhibit both high performance and excellent stability, featuring a low width-normalized SD resistance of about 10 Omega cm, a decent saturation mobility of 13 cm(2)/(V s), an off current below 1 x 10(-13) A, a threshold voltage of 0.5 V, a slight hysteresis of -0.02 V, and a less than 0.1 V threshold voltage shift under 30 V gate bias stresses for 2000 s.