An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS
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DOI：
10.1109/vlsic.2018.8502388
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发表时间：
2018-06
期刊：
影响因子：
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通讯作者：
Shouyi Yin;P. Ouyang;Jianxun Yang;Tianyi Lu;Xiudong Li;Leibo Liu;Shaojun Wei
中科院分区：
文献类型：
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作者：
Shouyi Yin;P. Ouyang;Jianxun Yang;Tianyi Lu;Xiudong Li;Leibo Liu;Shaojun Wei
采用28 nm工艺实现了一种用于深度神经网络的能效可重构处理器，该处理器具有二值/三值权值和1/2/4/8/16位激活。采用全部分像素求和(TPPS)、核变换数据重构(KTDR)和混合负载均衡机制(HLBM)三种技术来提高能量效率。测试结果表明，BWN的能效最高可达95.8top/w，TWN的能效最高可达95.1top/w，BNN的能效最高可达765.6 top/w，是目前最先进的能效的6.6倍。
An energy efficient reconfigurable processor for deep neural networks with binary/ternary weights and 1/2/4/8/16-bit activations is implemented in 28nm technology. Three technologies, Total- Partial- Pixel-Summation (TPPS), Kernel-Transformation-Data-Reconstruction (KTDR) and Hybrid Load-Balancing Mechanism (HLBM), are employed to improve energy efficiency. Measurement results show that the energy efficiency of at most 95.8 TOPS/w for BWN, and 95.1 TOPS/W for TWN and 765.6 TOPS/w for BNN is achieved, and it shows 6.6x higher over state-of-the-art works.