Power-centric design of high-speed I/Os
Power-centric design of high-speed I/Os
复制标题
以功耗为中心的高速 I/O 设计
DOI：
10.1145/1146909.1147130
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
C. Yang
中科院分区：
文献类型：
--
作者：
H. Hatamkhani;F. Lambrecht;V. Stojanović;C. Yang
随着芯片外总带宽超过太比特/秒（Tb/s），功耗是一个重要的设计考虑因素。此外，I/O链路的设计受到一组复杂的规范的约束，例如电压电平、电压噪声、信号确定性抖动、随机抖动、压摆率、BER等。这些规范导致电路和电路架构的复杂权衡，以最大限度地降低功耗。本文提出了一种设计框架，使权衡分析的I/O发射机的设计。该设计框架包括BER分析与信道模型耦合的逻辑规模优化，这是由所需的信令规范约束
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is constrained by a complex set of specifications such as voltage levels, voltage noise, signal deterministic jitter, random jitter, slew rate, BER etc. These specifications lead to complex tradeoffs for both circuits and circuit architecture in order to minimize power. This paper presents a design framework that enables the analysis of tradeoffs in the design of an I/O transmitter. The design framework includes BER analysis with a channel model coupled with logic sizing optimization that is constrained by the desired signaling specification