Full System Simulation and Verification Framework
Full System Simulation and Verification Framework
复制标题
完整的系统仿真和验证框架
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
Ying
中科院分区：
文献类型：
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作者：
Jing;Chen;C. Chang;C. Chen;Kuen;Y. Chu;J. Yeh;Ying
在本文中，我们提出了一个框架，以开发系统级别的高性能系统加速器硬件和相应的软件。该框架是通过集成虚拟机，电子系统级平台和增强的QEMU-SYSTEMC设计的。增强功能包括用于快速内存传输的本地主界面，以及用于启用完整系统仿真的软件/硬件通信的中断处理硬件。最后，PAC DSP核心被用作示例，以演示用于完整系统模拟的拟议框架。
In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.