Bounded Dataflow Networks and Latency-Insensitive circuits
Bounded Dataflow Networks and Latency-Insensitive circuits
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有界数据流网络和延迟不敏感电路
DOI：
10.1109/memcod.2009.5185393
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
Arvind Arvind
中科院分区：
文献类型：
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作者：
M. Vijayaraghavan;Arvind Arvind
提出了一种基于有界数据流网络的同步时序电路模块化精化理论。我们提供了一个程序，用于实现任何SSM到一个LI-BDN，一个特殊的类的BDNs具有一些良好的组成特性。我们发现，LI-BDNs的潜伏期不敏感的属性下的LI-BDNs的并行和迭代的组合物被保留。我们的理论允许人们在SSM中进行任意切割，并将每个部分变成LI-BDNF，而不会影响整体功能。我们可以进一步将每个组成LI-BDN细化为另一个LI-BDN，这可能需要不同数量的循环来计算。如果组分LI-BDN被正确地细化，我们保证整体行为相对于原始SSM将是周期准确的。因此，可以用单端口寄存器堆替换SSM中的3端口寄存器堆，而不影响SSM的正确性。我们给出了几个例子来说明我们的理论如何支持以前的技术的泛化延迟不敏感的细化SSM。
We present a theory for modular refinement of Synchronous Sequential Circuits (SSMs) using Bounded Dataflow Networks (BDNs). We provide a procedure for implementing any SSM into an LI-BDN, a special class of BDNs with some good compositional properties. We show that the Latency-Insensitive property of LI-BDNs is preserved under parallel and iterative composition of LI-BDNs. Our theory permits one to make arbitrary cuts in an SSM and turn each of the parts into LI-BDNs without affecting the overall functionality. We can further refine each constituent LI-BDN into another LI-BDN which may take different number of cycles to compute. If the constituent LI-BDN is refined correctly we guarantee that the overall behavior would be cycle-accurate with respect to the original SSM. Thus one can replace, say a 3-ported register file in an SSM by a one-ported register file without affecting the correctness of the SSM. We give several examples to show how our theory supports a generalization of previous techniques for Latency-Insensitive refinements of SSMs.