Bouncer: Static Program Analysis in Hardware
Bouncer: Static Program Analysis in Hardware
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DOI：
10.1145/3307650.3322256
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发表时间：
2019-06
期刊：
影响因子：
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通讯作者：
Joseph McMahan;Michael Christensen;Kyle Dewey;B. Hardekopf;T. Sherwood
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文献类型：
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作者：
Joseph McMahan;Michael Christensen;Kyle Dewey;B. Hardekopf;T. Sherwood
在讨论嵌入式系统的安全性和安全性时，我们通常将世界分为软件检查（静态或动态）或硬件检查（动态）。正如其他人指出的那样，硬件检查不仅提供效率。它们对设备的功能是固有的，因此是从电源上生存的。他们几乎不需要正确地依赖其他软件，并且由于它们直接连接到系统的操作中，因此难以绕过。我们探索了一个实验性的新嵌入式系统，该系统使用特殊用途的硬件进行静态分析，该系统可以防止所有具有内存错误，无效控制流以及其他几个不良属性的程序二进制文件。静态分析通常需要整个二元级别，而不是指导级的检查。我们表明，使用可用的刮擦式内存的精心构造的硬件状态计算机能够在流中有效检查功能二进制文件，并直接在硬件中直接在硬件中加载到嵌入式程序存储中。所得系统的系统非常小（不超过.0079 mm2），有效（能够以大约60个循环的平均吞吐量检查二进制文件），但可以保证从许多脆弱的行为中执行，从而导致安全性和安全性。安全问题。我们认为，这是第一次在硬件级别上实施任何静态分析，并为更复杂的硬件检查属性打开了大门。
When discussing safety and security for embedded systems, we typically divide the world into software checks (which are either static or dynamic) or hardware checks (which are dynamic). As others have pointed out, hardware checks offer more than just efficiency. They are intrinsic to the device's functionality and thus are live from power-up; they require little to no dependency on other software functioning correctly, and due to the fact they are wired directly into the operation of the system, are difficult or impossible to bypass. We explore an experimental new embedded system that uses special-purpose hardware for static analysis that prevents all program binaries with memory errors, invalid control flow, and several other undesirable properties from ever being loaded onto the device. Static analysis often requires whole-binary-level, rather than instruction-level, examination. We show that a carefully constructed hardware state machine, using available scratch-pad memory, is capable of efficiently checking functional binaries in a streaming and verifiably non-bypassable way directly in hardware as they are loaded into the embedded program store. The resulting system is surprisingly small (taking no more than .0079 mm2), efficient (capable of checking binaries at an average throughput of around 60 cycles per instruction), and yet guarantees execution free from many of the fragile behaviors that result in security and safety concerns. We believe this is the first time any static analysis has been implemented at the hardware level and opens the door to more complex hardware-checked properties.