Faster Born probability estimation via gate merging and frame optimisation
Faster Born probability estimation via gate merging and frame optimisation
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DOI：
10.22331/q-2022-10-13-838
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发表时间：
2022-02
期刊：
影响因子：
6.4
通讯作者：
Nikolaos Koukoulekidis;Hyukjoon Kwon;Hyejung H. Jee;D. Jennings;M. Kim
中科院分区：
文献类型：
--
作者：
Nikolaos Koukoulekidis;Hyukjoon Kwon;Hyejung H. Jee;D. Jennings;M. Kim
通过经典方法估计结果概率是验证量子计算设备的重要任务。任何量子电路的结果概率都可以使用蒙特卡罗采样来估计，其中电路帧表示中存在的负性的量量化了实现一定精度所需的样本数量的开销。在本文中，我们提出了两个经典的子例程：电路门合并和帧优化，优化电路表示，以减少采样开销。我们表明，这两个子例程的运行时规模多项式电路的大小和门的深度。我们的方法适用于一般的电路，无论生成门集，qudit尺寸和电路元件的选择框架表示。我们数值证明，我们的方法提供了改进的缩放的负开销的所有测试情况下的随机电路与Clifford+T和Haar随机门，我们的方法的性能相比，有利地与以前的准概率模拟器的非Clifford门的数量增加。
Outcome probability estimation via classical methods is an important task for validating quantum computing devices. Outcome probabilities of any quantum circuit can be estimated using Monte Carlo sampling, where the amount of negativity present in the circuit frame representation quantifies the overhead on the number of samples required to achieve a certain precision. In this paper, we propose two classical sub-routines: circuit gate merging and frame optimisation, which optimise the circuit representation to reduce the sampling overhead. We show that the runtimes of both sub-routines scale polynomially in circuit size and gate depth. Our methods are applicable to general circuits, regardless of generating gate sets, qudit dimensions and the chosen frame representations for the circuit components. We numerically demonstrate that our methods provide improved scaling in the negativity overhead for all tested cases of random circuits with Clifford+T and Haar-random gates, and that the performance of our methods compares favourably with prior quasi-probability simulators as the number of non-Clifford gates increases.