QPACE: power-efficient parallel architecture based on IBM PowerXCell 8i
QPACE: power-efficient parallel architecture based on IBM PowerXCell 8i
复制标题
QPACE：基于 IBM PowerXCell 8i 的高能效并行架构
DOI：
10.1007/s00450-010-0122-4
复制
发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Simon Heybrock
中科院分区：
文献类型：
--
作者：
H. Baier;H. Boettiger;M. Drochner;N. Eicker;U. Fischer;Z. Fodor;A. Frommer;Claude Gomez;G. Goldrian;Simon Heybrock
QPACE是一种针对点阵QCD模拟优化的新型大规模并行架构。每个节点包括一个IBM PowerXCell 8i处理器。节点通过在FPGA上实现的自定义三维环面网络相互连接。该架构在功耗方面进行了系统优化。这使得QPACE在2009年11月发布的Green500榜单上名列第一。在本文中，我们概述了该架构，并重点介绍了提高电源效率所采取的步骤。
QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. Each node comprises an IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus network implemented on an FPGA. The architecture was systematically optimized with respect to power consumption. This put QPACE in the number one spot on the Green500 List published in November 2009. In this paper we give an overview of the architecture and highlight the steps taken to improve power efficiency.