Analysis and optimization of the back-gate effect on lateral high-voltage SOI devices
Analysis and optimization of the back-gate effect on lateral high-voltage SOI devices
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DOI：
10.1109/ted.2005.850952
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发表时间：
2005-06
影响因子：
3.1
通讯作者：
S. Schwantes;T. Florian;T. Stephan;M. Graf;V. Dudek
中科院分区：
文献类型：
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作者：
S. Schwantes;T. Florian;T. Stephan;M. Graf;V. Dudek
首次讨论了背栅偏置对绝缘体上硅(SOI)衬底上横向DMOS(LDMOS)晶体管的影响。提出了考虑背栅偏置和器件参数的分析模型，并用0.8/SPLµ/m、80V SOI智能电源技术进行了验证。将解释，背栅偏置对LDPMOS器件的影响与LDnMOS晶体管直接相反。由于背栅的影响，p沟道和n沟道器件需要不同的设计策略来获得最佳的埋层厚度。提出了一种局部弱化背栅效应的新型器件结构，即体埋氧化层阶梯结构(BBOSS)。提出的新结构允许在不影响导通电阻的情况下对埋层厚度进行单独的优化。
This paper discusses for the first time the impact of the back-gate bias on lateral DMOS (LDMOS) transistors on silicon-on-insulator (SOI) substrates. An analytical model that takes the back-gate bias and the device parameters into account is presented and verified with a 0.8-/spl mu/m, 80-V SOI smart power technology. It will be explained that the effect of the back-gate bias on the LDPMOS devices is directly opposed to the LDnMOS transistors. The p-channel and the n-channel devices require different design strategies for the optimal buried oxide thickness due to the effect of the back-gate. A new device structure, namely body buried oxide step structure (BBOSS) that locally weakens the effect of the back-gate is presented. The proposed new structure allows a separated optimization of the buried oxide thickness without affecting the on-resistance.