Path delay estimation using power supply transient signals: a comparative study using Fourier and wavelet analysis
Path delay estimation using power supply transient signals: a comparative study using Fourier and wavelet analysis
复制标题
使用电源瞬态信号进行路径延迟估计：使用傅立叶和小波分析的比较研究
DOI：
10.1109/iccad.2003.159760
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
J. Plusquellic
中科院分区：
文献类型：
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作者：
Abhishek Singh;J. Tharian;J. Plusquellic
瞬态信号分析（TSA）是一种基于分析CMOS数字电路中由核心逻辑从电源焊盘中提取的动态（瞬态）电流（i/sub DDT/）的参数化器件测试技术。在之前的工作中，我们开发了一种测试程序，既可以用于检测由缺陷引起的信号变化，也可以用于获得无缺陷芯片中的延迟信息。利用离散傅里叶变换得到的瞬态信号相谱可以跟踪无缺陷芯片在大范围工艺变化下的路径延迟。然而，在最近的工作中，我们能够通过模拟实验，结合深亚微米晶体管模型，电路设计和路径敏化场景，证明我们现有的TSA方法无法产生准确的路径延迟预测。更具体地说，由两个具有广泛不同晶体管尺寸的逆变器链组成的电路显示出在一组最坏情况过程模型中产生弱相关的路径延迟。本文提出了一种基于小波的i/sub DDT/波形分析方法，以提高在这些条件下预测多路径延迟的准确性。
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (i/sub DDT/) drawn by the core logic from the power supply pads in a CMOS digital circuit. In previous work, we develop a test procedure that can be used both to detect signal variations caused by defects and to obtain delay information in defect free chips. Phase spectra of transient signals obtained using discrete Fourier transform are shown to track path delays of defect-free chips under a wide range of process variations. However, in recent work, we were able to demonstrate through simulation experiments incorporating deep submicron transistor models, a circuit design and path sensitization scenario in which our existing TSA method is not able to yield accurate predictions of path delays. More specifically, a circuit composed of two inverter chains constructed with widely varying transistor sizes was shown to produce path delays that were weakly correlated across a set of worst case process models. In this paper, an alternative wavelet-based analysis of i/sub DDT/ waveforms is shown to improve the accuracy of predicting multiple path delays under these conditions.