Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding
Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding
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DOI：
10.1109/tcsi.2013.2283779
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发表时间：
2014-04
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通讯作者：
Bo Yuan;K. Parhi
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文献类型：
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作者：
Bo Yuan;K. Parhi
由于其能力实现属性，极地代码已成为重要的误差校正代码。由于其复杂性低，连续的取消（SC）算法被视为极地解码器硬件设计的良好候选者。但是，对于（n，k）极性代码，（2N-2）的SC算法的长潜伏期是设计高通量极性解码器的瓶颈。在本文中，我们为SC解码的最后阶段介绍了一个新的重新重新制定。拟议的重新制定带来了两个好处。首先，在SC算法的最后阶段，关键路径和硬件复杂性大大降低。第二，可以同时解码2位而不是1位。结果，这种新解码器（称为2B-SC解码器）将延迟从（2n-2）降低到（1.5N-2）而不会丢失。此外，重叠的安排，预启动和前景技术用于设计两个额外的解码器，分别称为2B-SC越过拼盘的解码器和2b-SC-Sc-tecomponting解码器。在吞吐量和硬件效率方面，这三个架构都具有很大的优势。与已知的先前延迟SC解码器相比，2b-SC-temoctuont解码器的延迟降低了25％。合成结果表明，提出的（1024，512）2b-SC-SC-PROCOMPONTUNT解码器的吞吐量至少增加了4倍，硬件效率提高了40％。
Polar codes have emerged as important error correction codes due to their capacity-achieving property. Successive cancellation (SC) algorithm is viewed as a good candidate for hardware design of polar decoders due to its low complexity. However, for (n, k) polar codes, the long latency of SC algorithm of (2n-2) is a bottleneck for designing high-throughput polar decoder. In this paper, we present a novel reformulation for the last stage of SC decoding. The proposed reformulation leads to two benefits. First, critical path and hardware complexity in the last stage of SC algorithm is significantly reduced. Second, 2 bits can be decoded simultaneously instead of 1 bit. As a result, this new decoder, referred to as 2b-SC decoder, reduces latency from (2n-2) to (1.5n-2) without performance loss. Additionally, overlapped-scheduling, precomputation and look-ahead techniques are used to design two additional decoders referred to as 2b-SC-Overlapped-scheduling decoder and 2b-SC-Precomputation decoder, respectively. All three architectures offer significant advantages with respect to throughput and hardware efficiency. Compared to known prior least-latency SC decoder, the 2b-SC-Precomputation decoder has 25% less latency. Synthesis results show that the proposed (1024, 512) 2b-SC-Precomputation decoder can achieve at least 4 times increase in throughput and 40% increase in hardware efficiency.