SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation
SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation
复制标题
SACTA：一种适应热引起的延迟变化的自调节时钟树架构
DOI：
10.1109/tvlsi.2009.2023992
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发表时间：
2010
影响因子：
2.8
通讯作者：
Y. Ismail
中科院分区：
文献类型：
--
作者：
Jieyi Long;J. Ku;S. Memik;Y. Ismail
激进的技术规模缩小和低功耗设计技术导致分布式功率密度不均匀，这转化为芯片中的热流，导致空间和时间上的显著温度变化。为了缓解温度变化对电路时序的负面影响，我们提出了一种自调整时钟树结构SACTA，它执行与温度相关的动态时钟偏斜调度，以防止流水线电路中的时序违规。SACTA的动态和自适应功能由我们提出的温度可调的自动时滞缓冲器和温度不敏感的时滞缓冲器实现。这些特殊的延迟元件经过精心调整，以确保整个电路对温度变化的恢复能力。为了确定它们的配置，我们提出了一个高效和通用的时钟树设计和优化框架。此外，我们还证明SACTA适用于广泛的电路，包括多Vdd/Vth设计。实验结果表明，SACTA支持的管道能够在更大的工作温度范围内防止热致定时违规(平均而言，无违规范围可以提高15°C以上)。
Aggressive technology scaling down and low-power design techniques lead to uneven distributed power density, which translates into heat flow in the chips, causing significant temperature variations in both spatial and temporal terms. In order to mitigate the negative impacts of temperature variations on circuit timing, we propose SACTA, a self-adjusting clock tree architecture, which performs temperature-dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. The dynamic and adaptive features of SACTA are enabled by our proposed automatic temperature-adjustable skew buffers and temperature-insensitive skew buffers. These special delay elements are carefully tuned to ensure resilience of the entire circuit against temperature variation. To determine their configurations, we proposed an efficient and general clock tree design and optimization framework. Furthermore, we show that SACTA is applicable across a wide spectrum of circuits, including multi-Vdd/Vth designs. Experimental results show that a pipeline supported by SACTA is able to prevent thermal-induced timing violations within a significantly larger range of operating temperatures (on average, the violation-free range can be enhanced by over 15°C).