Pipelined Parallel FFT Architectures via Folding Transformation
Pipelined Parallel FFT Architectures via Folding Transformation
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DOI：
10.1109/tvlsi.2011.2147338
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发表时间：
2012-06
影响因子：
2.8
通讯作者：
M. Ayinala;M. J. Brown;K. Parhi
中科院分区：
文献类型：
--
作者：
M. Ayinala;M. J. Brown;K. Parhi
提出了一种快速傅立叶变换（FFT）并行流水线结构的设计方法。提出了一种基于折叠变换和寄存器最小化技术的FFT结构设计方法。推导出用于计算复值和真实的值快速傅里叶变换的新型并行流水线结构。对于复值傅立叶变换（CFFT），该结构利用串行结构中未充分利用的硬件，在不增加硬件复杂度L的情况下，推导出L-并行结构.所提出的架构的工作频率可以降低，这又降低了功耗。此外，本文提出了新的并行流水线架构的计算实值快速傅立叶变换（RFFT）。所提出的架构利用冗余的FFT样本的计算，以减少硬件的复杂性。所提出的设计和以前的架构之间的比较。在2并行CFFT和RFFT结构中，功耗分别可降低37%和50%。在所提出的架构中，以加扰的顺序获得输出样本。电路重新排序这些加扰的输出序列，以期望的顺序。
This paper presents a novel approach to develop parallel pipelined architectures for the fast Fourier transform (FFT). A formal procedure for designing FFT architectures using folding transformation and register minimization techniques is proposed. Novel parallel-pipelined architectures for the computation of complex and real valued fast Fourier transform are derived. For complex valued Fourier transform (CFFT), the proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. Further, this paper presents new parallel-pipelined architectures for the computation of real-valued fast Fourier transform (RFFT). The proposed architectures exploit redundancy in the computation of FFT samples to reduce the hardware complexity. A comparison is drawn between the proposed designs and the previous architectures. The power consumption can be reduced up to 37% and 50% in 2-parallel CFFT and RFFT architectures, respectively. The output samples are obtained in a scrambled order in the proposed architectures. Circuits to reorder these scrambled output sequences to a desired order are presented.