New techniques for speeding-up fault-injection campaigns
New techniques for speeding-up fault-injection campaigns
复制标题
加速断层注入活动的新技术
DOI：
10.1109/date.2002.998398
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发表时间：
2002
期刊：
影响因子：
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通讯作者：
C. López
中科院分区：
文献类型：
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作者：
L. Berrojo;Isabel González;Fulvio Corno;M. Reorda;Giovanni Squillero;L. Entrena;C. López
目前在几个主要应用领域需要容错电路，并且需要新一代CAD工具来自动化容错机制的插入和验证。本文概述了一种新的故障注入平台的特点及其在实际工业环境中的评价。故障注入平台主要用于评估ASIC和FPGA设计中实现的容错机制的正确性和有效性。该平台处理寄存器传输级的VHDL语言描述，然后综合这些描述，并基于商用工具进行VHDL语言的解析和模拟。它还详细介绍了在该平台内设计和实施的技术，以加快故障注入活动。给出了实验结果，显示了不同技术的效果，并表明它们能够将故障注入活动所需的总时间减少至少一个数量级。
Fault-tolerant circuits are currently required in several major application sectors, and a new generation of CAD tools is required to automate the insertion and validation of fault-tolerant mechanisms. This paper outlines the characteristics of a new fault-injection platform and its evaluation in a real industrial environment. The fault-injection platform is mainly used for assessing the correctness and effectiveness of the fault tolerance mechanisms implemented within ASIC and FPGA designs. The platform works on register transfer-level VHDL descriptions which are then synthesized, and is based on commercial tools for VHDL parsing and simulation. It also details techniques devised and implemented within the platform to speed-up fault-injection campaigns. Experimental results are provided, showing the effects of the different techniques, and demonstrating that they are able to reduce the total time required by fault-injection campaigns by at least one order of magnitude.