Systematic Scan Reconfiguration
Systematic Scan Reconfiguration
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DOI：
10.1109/aspdac.2007.358075
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发表时间：
2007-01
期刊：
影响因子：
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通讯作者：
Ahmad A. Al-Yamani;Narendra Devta-Prasanna;A. Gunda
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文献类型：
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作者：
Ahmad A. Al-Yamani;Narendra Devta-Prasanna;A. Gunda
我们提出了一种新的测试数据压缩技术，达到10倍至40倍的压缩比，而不需要从ATPG工具的任何信息，有关未指定的位。该技术适用于单卡以及过渡故障测试集。该技术允许积极的并行化扫描链，导致类似的减少测试时间。它还以类似的比例减少了测试器引脚要求。该技术是使用每个扫描链的几个门的硬件开销来实现的。
We present a new test data compression technique that achieves 10times to 40times compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain.