Fault Analysis Attack on an FPGA AES Implementation
Fault Analysis Attack on an FPGA AES Implementation
复制标题
对 FPGA AES 实施的故障分析攻击
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
Nidhal Selmane
中科院分区：
文献类型：
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作者：
F. Khelil;Mohamed Hamdi;S. Guilley;J. Danger;Nidhal Selmane
密码算法的硬件实现被广泛用于保护无线网络。它们以较低的处理和能源成本保证了良好的安全性能。然而，与传统实现不同，它们容易受到侧信道攻击。特别地，故障攻击已经证明了它们在破解一些健壮的对称和非对称加密算法的硬件实现方面的有效性。在本文中，我们开发了一个FPGA版本的Piret和Quisquater对AES（高级加密标准）算法提出的攻击。通过对受故障注入过程影响的轮次的时间和空间分析，我们将上述攻击适应于我们的上下文。本文的研究结果可以为设计一个更安全的AES的FPGA实现。
Hardware implementation of cryptographic algorithms are widely used to secure wireless networks. They guarantee good security performance at low processing and energy costs. However, unlike traditional implementations, they are vulnerable to side channel attacks. Particularly, fault attacks have proved their efficiency in cracking hardware implementation of some robust symmetric and asymmetric encryption algorithms. In this paper, we develop an FPGA version of the attack proposed by Piret and Quisquater against the AES (Advanced Encryption Standard) algorithm. Through temporal and spatial analyses of the rounds that have been affected by the fault injection process, we adapt the aforementioned attack to our context. The results obtained in this paper can serve to design a more secure FPGA implementation of AES.