Practical Setup Time Violation Attacks on AES
Practical Setup Time Violation Attacks on AES
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DOI：
10.1109/edcc-7.2008.11
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发表时间：
2008-05
期刊：
影响因子：
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通讯作者：
Nidhal Selmane;S. Guilley;J. Danger
中科院分区：
文献类型：
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作者：
Nidhal Selmane;S. Guilley;J. Danger
故障攻击是破解AES和DES等健壮密码算法的有力工具。密码系统的各种故障攻击方法已经被发现和研究。然而，据作者所知，迄今为止发表的所有攻击都使用了故障的理论模型。本文证明了我们能够在实验上重现G。Piret和J.J.Quisquater（2003）提出了一种对嵌入AES加密器的智能卡进行低功耗故障注入的方法，尽管这种方法是一种方便的故障注入技术，但在公开文献中并不常见。我们认为，故障模型是一致的设置违反：错误出现在组合逻辑锥，在向下寄存器中的早期采样所造成的结束。我们还进行了广泛的故障表征，在空间和时间定位方面。
Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES and DES. Various methods of faults attack on cryptographic systems have been discovered and researched. However, to the authors' knowledge, all the attacks published so far use a theoretical model of faults. In this paper we prove that we are able to reproduce experimentally the random errors model used by G. Piret and J.J. Quisquater (2003) to realize practical fault attack on a smart card embedding an AES encryptor by under-powering it. In spite of the fact that this method is a convenient fault injection technique to set up, it does not often appear in the open literature. We argue that the fault model is consistent with a setup violation: errors appear at the end of combinatorial logic cones, caused by an early sampling in the downwards registers. We also carry out an extensive characterization of the faults, in terms of spatial and temporal localization.