Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array
Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array
复制标题
异步蜂窝逻辑网络作为通用大规模并行阵列的协处理器
DOI：
10.1002/cta.679
复制
发表时间：
2011
影响因子：
2.3
通讯作者：
P. Dudek
中科院分区：
文献类型：
--
作者：
A. Lopich;P. Dudek
本文演示了异步蜂窝处理器阵列的实现，该阵列有助于二进制触发波传播，广泛用于各种图像处理算法。该电路工作在连续时间模式下，可实现高工作性能和低功耗。采用0.35µm三金属CMOS工艺制造了具有24×60单元概念验证阵列的集成电路并进行了测试。二进制波传播单元仅占用16×8µm2，设计用作通用处理器每像素阵列中的协处理器，用于焦平面图像处理。给出了物体重构和孔洞填充等全局操作的结果。版权所有© 2010约翰威利父子有限公司.
This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm2 the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.