A Programmable and Configurable Mixed-Mode FPAA SoC
A Programmable and Configurable Mixed-Mode FPAA SoC
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DOI：
10.1109/tvlsi.2015.2504119
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发表时间：
2016-06-01
影响因子：
2.8
通讯作者：
Ramakrishnan, Shubha
中科院分区：
文献类型：
--
作者：
George, Suma;Kim, Sihwan;Ramakrishnan, Shubha
提出了一种基于浮栅(FG)、现场可编程模拟阵列(FPAA)的片上系统(SoC)，它集成了模拟和数字可编程和可配置模块和16位开源MSP430微处理器(MUP)及其接口电路。我们给出了FPAA SoC体系结构、编译到该体系结构中的一系列电路的实验结果以及系统测量。在FPAA SoC上编译的模拟声学命令字分类器需要23µWTO来实验识别TIMIT数据库短语中的单词Dark。本文联合优化了高参数密度(归一化的可编程元件/区域/过程的数量)，以及由于其数据流处理而具有的计算的高可访问性；SoC FPAA的密度是其他非FG方法的600 000倍。
This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (mu P) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 mu Wto experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 000x higher density than other non-FG approaches.