Persistent Memory Research in the Post-Optane Era
Persistent Memory Research in the Post-Optane Era
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DOI：
10.1145/3609308.3625268
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发表时间：
2023-10
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影响因子：
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通讯作者：
Peter Desnoyers;Ian Adams;Tyler Estro;Anshul Gandhi;Geoff Kuenning;Mike Mesnier;Carl Waldspurger;Avani Wildani;E. Zadok
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作者：
Peter Desnoyers;Ian Adams;Tyler Estro;Anshul Gandhi;Geoff Kuenning;Mike Mesnier;Carl Waldspurger;Avani Wildani;E. Zadok
在研究人员对持久性内存（PMem）的到来进行了十多年的预期之后，基于3D XPoint的英特尔Optane内存在2019年的首批出货量很快就在2022年被取消。这是另一个想法迅速从未来走向过去的例子，把这个领域的工作放在失败技术的墓地吗？最近推出的Compute Express Link（CXL）可能提供了一条前进的道路，其持久内存配置文件提供了一个通用的PMem连接点。然而，存储器速度持久性的新技术似乎还需要几年时间，而且可能永远无法与不断发展的DRAM和闪存速度竞争。如果没有持久内存本身，未来的PMem研究是否注定要失败？我们提供了两个参数，为什么死亡的PMem研究的报告被大大夸大。首先，大部分持久性内存研究实际上并没有解决内存持久性，而是内存崩溃一致性，这在CPU无法观察崩溃后内存状态的以前系统中从来都不是问题。CXL内存池允许多个主机共享一个内存，所有主机都在不同的故障域中，即使使用易失性内存也会引起崩溃一致性问题。其次，我们认为CXL需要一个“分解”的PMem研究。迄今为止，大多数工作都假设了一种单一的技术和一组功能，即，速度、字节寻址能力和CPU加载/存储访问。由于开放接口允许新的拓扑结构和不同的PMem技术，我们认为需要单独或组合检查这些功能。虽然一种形式的PMem可能已经被取消，我们认为，它提出的研究问题不仅仍然相关，但在CXL为基础的未来扩大。
After over a decade of researcher anticipation for the arrival of persistent memory (PMem), the first shipments of 3D XPoint-based Intel Optane Memory in 2019 were quickly followed by its cancellation in 2022. Was this another case of an idea quickly fading from future to past tense, relegating work in this area to the graveyard of failed technologies? The recently introduced Compute Express Link (CXL) may offer a path forward, with its persistent memory profile offering a universal PMem attachment point. Yet new technologies for memory-speed persistence seem years off, and may never become competitive with evolving DRAM and flash speeds. Without persistent memory itself, is future PMem research doomed? We offer two arguments for why reports of the death of PMem research are greatly exaggerated. First, the bulk of persistent-memory research has not in fact addressed memory persistence, but rather in-memory crash consistency, which was never an issue in prior systems where CPUs could not observe post-crash memory states. CXL memory pooling allows multiple hosts to share a single memory, all in different failure domains, raising crash-consistency issues even with volatile memory. Second, we believe CXL necessitates a "disaggregation" of PMem research. Most work to date assumed a single technology and set of features, i.e., speed, byte addressability, and CPU load/store access. With an open interface allowing new topologies and diverse PMem technologies, we argue for the need to examine these features individually and in combination. While one form of PMem may have been canceled, we argue that the research problems it raised not only remain relevant but have expanded in a CXL-based future.