Integrated VDMOS transistor with reduced JFET effect
Integrated VDMOS transistor with reduced JFET effect
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DOI：
10.1109/essder.2006.307692
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发表时间：
2006-09
期刊：
影响因子：
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通讯作者：
H. Hakim;D. Bolognesi;F. De Pestel
中科院分区：
文献类型：
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作者：
H. Hakim;D. Bolognesi;F. De Pestel
为了改善集成VDMOS晶体管的击穿电压和导通电阻之间的折衷，已引入了一种反结场效应注入器，用于基于0.35 μ m CMOS节点的80V智能功率平台。优化的剂量和能量允许在不显著影响击穿电压和该技术的其他集成组件的情况下降低电阻
In order to improve the trade-off between the breakdown voltage and the on-state resistance of integrated VDMOS transistors, an anti junction field effect implant has been introduced for an 80V smart power platform based on a 0.35 mum CMOS node. Optimized dose and energy allow a reduction of the resistance without significant impact on the breakdown voltage and the other integrated components of the technology