Beat Frequency Detector--Based High-Speed True Random Number Generators: Statistical Modeling and Analysis
Beat Frequency Detector--Based High-Speed True Random Number Generators: Statistical Modeling and Analysis
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基于拍频检测器的高速真随机数发生器：统计建模和分析
DOI：
10.1145/2866574
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
K. Parhi
中科院分区：
文献类型：
--
作者：
Yingjie Lao;Qianying Tang;C. Kim;K. Parhi
真随机数发生器（TRNG）是保证密码系统安全的关键部件。与伪随机数发生器（PRNG）相比，TRNG通过从物理现象中提取随机性来提供更高的安全性。为了评估TRNG，应该研究电路模型和原始比特流的统计特性。本文提出了一种基于差频检测器的高速真随机数发生器（BFD-TRNG）模型。该模型的参数是从测试芯片的实验数据中提取的。对所提出的模型进行统计分析，以获得TRNG计数器值的均值和方差。我们的统计分析结果表明，计数器值的平均值是成反比的两个环形振荡器（ROSC）的频率差，而计数器值的动态范围与环境噪声的标准偏差线性增加，并随着频率差的增加而减小。如果没有来自测试数据的测量，就无法创建模型;同样，如果没有模型，就无法预测TRNG的性能。所提出的方法的关键贡献在于拟合模型的测量数据和使用该模型来预测性能的BFD-TRNG，还没有制造的能力。还提出了几种新的替代BFD-TRNG架构，包括并行BFD，级联BFD和并行级联BFD。这些TRNG使用所提出的模型进行了分析，它表明，并行BFD结构需要更少的单位面积，而级联BFD结构具有更大的动态范围，同时保持相同的平均计数器值作为原始的BFD-TRNG。它示出，3.25M和4 M的随机比特可以从并行BFD和并行级联BFD，分别获得每个计数器值，其中M个计数器值并行计算。此外，统计分析结果表明，BFD-TRNG具有更好的随机性和更低的单位比特成本比其他现有的ROSC-TRNG设计。例如，它表明，BFD-TRNG积累150%以上的抖动比原来的两个振荡器TRNG和并行BFD-TRNG需要三分之一的权力和一半的面积为相同数量的随机位的指定周期。
True random number generators (TRNGs) are crucial components for the security of cryptographic systems. In contrast to pseudo--random number generators (PRNGs), TRNGs provide higher security by extracting randomness from physical phenomena. To evaluate a TRNG, statistical properties of the circuit model and raw bitstream should be studied. In this article, a model for the beat frequency detector--based high-speed TRNG (BFD-TRNG) is proposed. The parameters of the model are extracted from the experimental data of a test chip. A statistical analysis of the proposed model is carried out to derive mean and variance of the counter values of the TRNG. Our statistical analysis results show that mean of the counter values is inversely proportional to the frequency difference of the two ring oscillators (ROSCs), whereas the dynamic range of the counter values increases linearly with standard deviation of environmental noise and decreases with increase of the frequency difference. Without the measurements from the test data, a model cannot be created; similarly, without a model, performance of a TRNG cannot be predicted. The key contribution of the proposed approach lies in fitting the model to measured data and the ability to use the model to predict performance of BFD-TRNGs that have not been fabricated. Several novel alternate BFD-TRNG architectures are also proposed; these include parallel BFD, cascade BFD, and parallel-cascade BFD. These TRNGs are analyzed using the proposed model, and it is shown that the parallel BFD structure requires less area per bit, whereas the cascade BFD structure has a larger dynamic range while maintaining the same mean of the counter values as the original BFD-TRNG. It is shown that 3.25M and 4M random bits can be obtained per counter value from parallel BFD and parallel-cascade BFD, respectively, where M counter values are computed in parallel. Furthermore, the statistical analysis results illustrate that BFD-TRNGs have better randomness and less cost per bit than other existing ROSC-TRNG designs. For example, it is shown that BFD-TRNGs accumulate 150% more jitter than the original two-oscillator TRNG and that parallel BFD-TRNGs require one-third power and one-half area for same number of random bits for a specified period.