Hardware-Based Aging Mitigation Scheme for Memory Address Decoder
Hardware-Based Aging Mitigation Scheme for Memory Address Decoder
复制标题
基于硬件的内存地址解码器老化缓解方案
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
F. Catthoor
中科院分区：
文献类型：
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作者：
Daniel Kraak;I. Agbo;M. Taouil;S. Hamdioui;P. Weckx;S. Cosemans;F. Catthoor
设计师通常会在存储器中添加设计余量以补偿其老化。随着技术规模的扩大，老龄化的影响越来越大，更大的利润变得必要。然而，这会对面积、产量、性能和功耗产生负面影响。或者，可以使用缓解方案来减少老化的影响。本文提出了一种基于硬件的缓解方案的存储器的地址解码器逻辑。该方案是基于适应解码器的工作量在空闲周期期间强调短路径，并把长路径进入放松。由于工作负载经过调整，老化对地址解码器的影响得以减少，从而实现更可靠的内存。为了验证缓解方案的好处，解码器的降级的L1数据和指令缓存的ARM v8-a处理器进行了分析。实验结果表明，所提出的缓解方案减少了高达4.1倍的解码器的时序裕度的退化在可忽略的面积和不超过3%的功耗开销。
Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.