Chip Last Fanout Chip on Substrate (FOCoS) Solution for Chiplets Integration
Chip Last Fanout Chip on Substrate (FOCoS) Solution for Chiplets Integration
复制标题
用于小芯片集成的芯片最后扇出基板上芯片 (FOCoS) 解决方案
DOI：
10.1109/ectc51906.2022.00309
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发表时间：
2022
期刊：
影响因子：
--
通讯作者：
You
中科院分区：
文献类型：
--
作者：
T. Lee;Shu;Hsin;You
在目前的电子产品市场中，高密度的小芯片封装集成正走向“超过摩尔”的世界。由于从大芯片分解，多芯片架构提供了高性能和低成本的电子产品。这些软件包是为服务器、高性能计算、路由器和交换机市场开发的。因此，高带宽存储器（HBM）器件或多个ASIC管芯的集成需要高I/O计数和信号传输。针对这种封装要求，采用芯片后扇出基板上芯片（CL-FOCoS）技术将多个小芯片集成到单个封装中。高I/O密度能力提供了高性能要求的灵活性。此外，芯片最后工艺导致较低的不良管芯损耗和较低的电子生产总成本。提出了一种用于小芯片集成的先进扇出解决方案。多个ASIC（包括一个具有8个小芯片的大ASIC）被倒装芯片附接在扇出晶片上以形成扇出芯片（FOC）。FOC是一个更大尺寸的模块（与原始ASIC尺寸相比），它总共包含9个ASIC，然后进行倒装芯片工艺附着在有机基板上（基板上工艺），完成最终封装。采用芯片最后方法，即在ASIC附着之前制造多层RDL并确保质量。扇出工艺包含3层RDL，最小L/S为2/2um，采用堆叠或交错通孔工艺。对于扇出型RDL工艺，钝化过孔和细线RDL将更好地控制CD变化和质量，通过AOI和电测量，如RDL泄漏，方块电阻和过孔链电阻来判断。为了满足高性能的要求，ASIC中设计了混合凸块（大凸块间距和小凸块间距）。小凸块间距应用于管芯到管芯接口中以满足高密度互连要求。对于晶圆上芯片（CoW）和基板上芯片（CoS）组装工艺，扇出晶圆可以更好地控制晶圆级翘曲，而平坦的晶圆有助于混合Ubump连接。另一方面，在基板上的扇出芯片将更好的连接质量和CoS封装翘曲控制加强环。经过温度循环测试，全封装具有良好的可靠性。
In recent electronic product market, high density chiplet package integration is taking leads to the world of "more than Moore". Since breaking down from a large chip, multi-chip architectures provide high performance and low cost of electronic production. These packages are developed for the server, high performance computing, router, and switcher markets. Therefore, the integration of high bandwidth memory (HBM) devices or multiple ASIC dies requires high I/O counts and signal transmitting. For this package requirement, chip last fanout chip on substrate (CL-FOCoS) technology is adopted to integrate multiple chiplets into a single package. The high I/O density capability provides the flexibility of high performance requirement. Moreover, the chip last process induces lower non-good die loss and lower total cost of electronic production. Advanced fanout solution for chiplets integration is presented in this paper. Multiple ASICs, which includes one large ASIC with 8 small chiplets, are flip chip attached on a fanout wafer to form a fanout Chip (FOC). The FOC is a much larger size module (vs. original ASIC size), which contains 9 ASICs in total, then carry on the flip chip process to attach on an organic substrate (on substrate process), to complete the final package.Chip last approach is adopted, meaning multi layers RDL is fabricated and ensure good quality, prior to ASIC attach. The fanout process contains 3 layers of RDL with min. L/S of 2/2um, with stacking or stagger via process. Regarding fanout RDL process, the passivation via and fine line RDL would be better control on CD variation and quality judge by AOI and electric measurement, such as RDL leakage, sheet resistance and via chain resistance. For high performance requirement, hybrid bump (large and small bump pitch) is designed in ASICs. Small bump pitch is applied in the die-to-die interface for high density interconnect requirements. Large bump pitch is designed for outside communication from FOC.Regarding chip on wafer (CoW) and chip on substrate (CoS) assembly process, the fanout wafer would be better control on wafer level warpage and flatness wafer will helpful for hybrid ubump joint. On the other hand, fanout chip on substrate would be better on joint quality and CoS package warpage control by stiffener ring. After temperature cycling test, a good reliability performance of full package is demonstrated.