Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT
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DOI：
10.1109/tii.2021.3106242
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发表时间：
2022-05
影响因子：
12.3
通讯作者：
Tao Li;Yitao Ma;Ko Yoshikawa;O. Nomura;T. Endoh
中科院分区：
文献类型：
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作者：
Tao Li;Yitao Ma;Ko Yoshikawa;O. Nomura;T. Endoh
将空前增长的数据转移到边缘是工业物联网（IIoT）时代的主流趋势，将对我们日常生活的方方面面产生深远的影响，包括交通、医疗保健和娱乐。然而，在边缘处进行大量的数据分析和处理将不可避免地增加边缘处理器的负担，并大大增加其设计复杂度和能耗。本文提出了一种灵活的基于位调整的节能卷积模块，该模块具有近似分治（ADC）乘法器，用于紧凑和低功耗边缘处理器设计。利用最大分布搜索技术为卷积模块的输入和输出寻找最优的不动点表示格式。神经网络显示出与部署确定的表示格式的32b浮点乘法相同的精度。通过消除权值和特征映射之间的高比特乘法，提出了一种ADC乘法器来实现卷积模块。采用$Q(6,9)$输入和$Q(7,8)$输出表示格式的基于ADC乘法器的卷积模块的动态功耗比16-b有符号乘法电路低3.85%。此外，如果输出用Q(1,14)$格式表示，那么对于16-b卷积，使用Q(6,9)$输入的动态功耗能够降低15.38%，对于64-b乘法，动态功耗可以降低39.93%。卷积模块在现场可编程门阵列评估板上的实际验证系统具有突出的低功耗特性。
Offloading the unprecedented growing data to the edge exhibits a mainstream trend in the Industrial Internet of Things (IIoT) era, delivering far-reaching impacts in all aspects of our daily lives, including transportation, health care, and entertainment. However, voluminous data analyzes and processing at the edge will unavoidably raise the edge processor's burden and dramatically expand its design complexity and energy dissipation. This article proposes a flexible bit-adjustment-based energy-efficient convolution module with an approximate divide-and-conquer (ADC) multiplier for compact and low-power edge processor design. The maximum distribution search technique is utilized to exploit the optimal fixed-point representation format for both input and output of the convolution module. The neural network manifests the same precision as a 32-b floating-point multiplication deploying the determined representation formats. An ADC multiplier is proposed to realize the convolution module by eliminating the high-bit multiplication between weights and feature maps. The dynamic power consumption of the ADC multiplier-based convolution module with the $Q(6, 9)$ input and $Q(7, 8)$ output representation formats is 3.85% lower than that of the 16-b signed multiplication circuit. Furthermore, the dynamic power consumption with $Q(6, 9)$ input is capable of being decreased by 15.38% for the 16-b convolution if the output is represented by the $Q(1, 14)$ format and by up to 39.93% for the 64-b multiplication. The practical verification system of the convolution module working on a field-programmable gate array evaluation board exhibits an outstanding low-power characteristic.