Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud
Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud
复制标题
减轻对云中安全多租户 FPGA 的电气级攻击
DOI：
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复制
发表时间：
2019
影响因子：
2.3
通讯作者：
M. Tahoori
中科院分区：
文献类型：
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作者：
Jonas Krautter;Dennis R. E. Gnad;M. Tahoori
越来越多的趋势是使用多租户fpga，特别是在云环境中，其中硬件的部分访问权被授予多个第三方。这导致了fpga中的新型攻击，这些攻击不仅在逻辑层面上运行，而且通过共同的电力输送网络在电气层面上运行。由于fpga是从软件端配置的，因此攻击者可以从软件端发起硬件攻击，从而影响整个系统的安全性。在本文中，我们将展示针对电气级攻击的对策的第一次尝试，该对策基于位流检查方法。比特流被转换回平面技术映射的网络列表，然后检查显示FPGA逻辑潜在恶意运行时行为的属性。我们的方法可以提供FPGA位流用于针对FPGA结构或整个SoC平台的其他用户的主动故障或被动侧通道攻击的潜在风险度量。
A rising trend is the use of multi-tenant FPGAs, particularly in cloud environments, where partial access to the hardware is given to multiple third parties. This leads to new types of attacks in FPGAs, which operate not only on the logic level, but also on the electrical level through the common power delivery network. Since FPGAs are configured from the software-side, attackers are enabled to launch hardware attacks from software, impacting the security of an entire system. In this article, we show the first attempt of a countermeasure against attacks on the electrical level, which is based on a bitstream checking methodology. Bitstreams are translated back into flat technology mapped netlists, which are then checked for properties that indicate potential malicious runtime behavior of FPGA logic. Our approach can provide a metric of potential risk of the FPGA bitstream being used in active fault or passive side-channel attacks against other users of the FPGA fabric or the entire SoC platform.