An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches
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DOI：
10.1109/tmscs.2018.2827955
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发表时间：
2018-10
期刊：
影响因子：
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通讯作者：
Masayuki Sato;Yoshiki Shoji;Zentaro Sakai;Ryusuke Egawa;Hiroaki Kobayashi
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文献类型：
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作者：
Masayuki Sato;Yoshiki Shoji;Zentaro Sakai;Ryusuke Egawa;Hiroaki Kobayashi
自旋转移扭矩随机存储器(STT-RAM)作为未来微处理器末级高速缓冲存储器(LLC)的关键器件，受到了广泛的关注。由于STT-RAM具有比SRAM更高的密度和非易失性，因此STT-RAM可以帮助构建具有更大容量和更低静态能量的高速缓冲存储器。然而，由于STT-RAM在存储数据时改变其磁化状态，因此对STT-RAM LLC的写访问请求的能量成本比SRAM LLC的更昂贵。因此，写入密集型应用的STT-RAM LLC的总能耗可能会增加。针对这一问题，本文提出了一种邻行合并回写方案。由于STT-RAM高速缓存的较大高速缓存线可以有助于降低每字节的写入能量成本，因此上级高速缓存将两个相邻的小线合并为一个大线，然后将合并的线写回STT-RAM LLC。此外，LLC的较大线路尺寸导致静态能量成本的降低。评估结果表明，该方案可以将STT-RAM LLC的能耗降低高达26%，平均降低9.3%。
Spin-Transfer Torque RAM (STT-RAM) has attracted attention as a key element for the Last-Level Cache (LLC) of a future microprocessor. Since STT-RAM has a higher density than SRAM and non-volatility, STT-RAM can contribute to building the cache memory with a larger capacity and a less static energy. However, since STT-RAM changes its magnetization state in the case when storing data, the energy cost of write access requests for an STT-RAM LLC is more expensive than that of an SRAM LLC. As a result, the total energy consumption of the STT-RAM LLC for write-intensive applications may increase. To solve this problem, this paper proposes an Adjacent-Line-Merging Writeback Scheme. Since a larger cache line of an STT-RAM cache can contribute to the reduction in the write energy cost per byte, the upper-level cache merges two adjacent small lines to one large line, and then writes the merged line back to the STT-RAM LLC. Moreover, the larger line size for the LLC leads to a reduction in the static energy cost. The evaluation results show that the proposed scheme can reduce the energy consumption of the STT-RAM LLC by up to 26, and 9.3 percent on average.