Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors
Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors
复制标题
适用于在多核处理器上运行的异构时间关键工作负载的可预测总线仲裁方案
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发表时间：
2011
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通讯作者：
P. Sainrat
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作者：
Roman Bourgade;Christine Rochange;P. Sainrat
多核架构现在被认为是实现未来时间关键型嵌入式系统的可能候选者。挑战在于使每个任务的最坏情况执行时间（WCET）可预测。在本文中，我们研究了总线仲裁方案与上限总线延迟。我们专注于异构的工作负载，其中的任务表现出不同的带宽要求。所提出的方案执行两级仲裁：核心被组织成组，在同一组中的所有核心受益于相同的带宽。不同的算法被认为是共享组之间的总线槽。实验结果（WCET估计）表明，改进的全球WCET相比，通常的循环计划。这将增强异构任务集的可并行性。
Multi-core architectures are now considered as possible candidates to implement future time-critical embedded systems. The challenge is to make the worst-case execution time (WCET) of each task predictable. In this paper, we investigate bus arbitration schemes with upper-bounded bus latencies. We focus on heterogeneous workloads in which tasks exhibit distinct requirements in terms of bandwidth. The proposed schemes perform a two-level arbitration: the cores are organized into groups and all the cores in the same group benefit from the same bandwidth. Different algorithms are considered to share the bus slots among the groups. Experimental results (WCET estimates) show an improved global WCET compared to usual round-robin schemes. This will enhance the schedulability of heterogeneous task sets.