Time evolution of temperature distribution of a flip-chip no-flow underfill package during solder reflow process
Time evolution of temperature distribution of a flip-chip no-flow underfill package during solder reflow process
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DOI：
10.1109/ectc.2003.1216315
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发表时间：
2003-05
期刊：
影响因子：
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通讯作者：
Zhuqing Zhang;A. Voyakunpinij;S. Sitaraman;C. Wong
中科院分区：
文献类型：
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作者：
Zhuqing Zhang;A. Voyakunpinij;S. Sitaraman;C. Wong
有机基板上的倒装芯片依靠底部填充来重新分布热机械应力并增强焊点可靠性。然而，传统的倒装芯片底部填充工艺涉及多个工艺步骤，已成为倒装芯片工艺的瓶颈。无流动底部填充的发明是为了简化倒装芯片底部填充工艺并降低封装成本。无流动底部填充工艺要求底部填充胶具有较高的固化潜伏期，以避免在焊料回流之前凝胶化，从而确保焊料互连。因此，无流动倒装芯片封装在回流焊过程中的温度分布对于高组装良率非常重要。本文使用有限元方法 (FEM) 对倒装芯片无流动底部填充封装在回流焊过程中的温度分布进行建模。使用 DSC 研究获得的自催化反应模型建立了底部填充固化动力学。开发了两种方法，以便使用迭代和循环程序将底部填充胶的固化动力学纳入 FEM 模型中。研究了整个封装和底部填充层的温度分布。讨论了底部填充圆角存在的影响以及芯片尺寸对底部填充层温差的影响。还评估了底部填充固化动力学对建模结果的影响。
Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.